The present invention relates to a logic operation algorithm applicable to the execution of a logic operation, and more particularly to a logic operation algorithm in which conventional logic gates are not used and the logic operations are performed using a difference in times taken while operands arrive at a specific circuit.
FIG. 1 is a block diagram for schematically describing a relationship between the conventional methods for embodying several logic circuits and a race logic circuit of the present invention.
Up to the now, all the digital circuits have used logic devices in order to perform logic operations. These logic devices are realized by integrated circuits (ICs). There are several methods in realizing a single logic device. For instance, there are a static circuit realization method, a dynamic circuit realization method and so on.
Since these respective realization methods have a difference in operation speed, power consumption amount, area occupied in an integrated circuit, etc., they show different performance from each other.
In case of realizing an integrated circuit system, selecting a proper logic circuit realization method allows a system in accordance with a designer""s intention to be realized.
In recent years, as various types of logic circuit realization methods are provided, performance of logic devices is enhanced and their characteristics are also diversified.
However, in the use of the logic devices, there are two problems basically. One is a delay time due to the use of transistor. Since logic device uses transistor in order to perform logic operation, time delay generated by the transistor is basically inevitable. Due to the advancement in IC process technologies, there appears a tendency toward decrease in the delay time, but the transistor still has a finite delay time. Such a delay time is inevitable in all logic circuits of performing logic operation.
The other problem is a delay time in interconnection line, which is generated due to the increase in the integrity of the ICs. Increase in the integrity decreases the interval between interconnection lines in ICs, resulting in the increase in the parasitic capacitance that is generated between the interconnection lines. Because of this, the time delay due to the interconnection lines also occupies a considerable portion in a time spent in performing a logic operation.
Due to these problems, if a logic circuit is realized by a logic device composed of transistors, no matter how fast logic circuit realization method is developed, the logic circuit can not be operated in a speed faster than the delay time due to the transistors and the delay time due to the interconnection lines.
Accordingly, it is an object of the present invention to develop a logic operation method that is different from the conventional method using a logic device and thus provide a new methodology in the logic operation.
It is another object of the present invention to overcome the delay time problem due to the transistors and the interconnection lines and thus actively use waste of the delay time.
To accomplish the above objects, there is provided a race logic circuit including: a WTA circuit for receiving an operand logic signal and outputting only a high signal which is the first to arrive among the operand logic signals; multiple race lines for inputting the operand logic signal into the WTA circuit; a clock distribution line having multiple delay devices connected in series, both ends of the respective delay devices being connected to a triggering line, the clock distribution line receiving an external clock and outputting a triggering signal into the triggering line; and multiple operand logic signal input switches which are triggered by the triggering signal output from the triggering line, for deciding whether to input the operand logic signal into the race line or not.